NTD4302
Power MOSFET
68 A, 30 V, N−Channel DPAK/IPAK
Features
•
•
•
•
•
•
•
•
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
IDSS Specified at Elevated Temperature
DPAK Mounting Information Provided
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
V(BR)DSS
RDS(on) TYP
ID MAX
30 V
7.8 mW @ 10 V
68 A
D
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery Powered Products:
N−Channel
G
S
i.e., Computers, Printers, Cellular and Cordless Telephones,
and PCMCIA Cards
4
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
4
Unit
VDSS
30
Vdc
Gate−to−Source Voltage − Continuous
VGS
±20
Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Continuous Drain Current @ TC = 25°C (Note 4)
Continuous Drain Current @ TC = 100°C
RqJC
PD
ID
ID
1.65
75
68
43
°C/W
W
A
A
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 3)
RqJA
PD
ID
ID
IDM
67
1.87
11.3
7.1
36
°C/W
W
A
A
A
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 3)
RqJA
PD
ID
ID
IDM
120
1.04
8.4
5.3
28
°C/W
W
A
A
A
Operating and Storage Temperature Range
TJ, Tstg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc,
Peak IL = 17 Apk, L = 5.0 mH, RG = 25 W)
EAS
722
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
TL
°C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
4. Current Limited by Internal Lead Wires.
1
1 2
3
DPAK
CASE 369C
(Surface Mount)
STYLE 2
2
3
IPAK
CASE 369D
(Straight Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
AYWW
T
4302G
Drain−to−Source Voltage
AYWW
T
4302G
Rating
2
1
3
Drain
Gate
Source
A
Y
WW
T4302
G
1 2 3
Gate Drain Source
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1
Publication Order Number:
NTD4302/D
