HY57V56820(L)T
4Banks x 8M x 8Bit Synchronous DRAM
DESCRIPTION
The HY57V56820T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V56820 is organized as 4 banks of 8,388,608x8.
HY57V56820T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3V ± 0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
8192 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 and Full Page for Sequential Burst
•
•
Data mask function by DQM.
•
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Internal four banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V56820T-HP
125MHz
HY57V56820T-P
HY57V56820LT-HP
133MHz
HY57V56820LT-H
125MHz
HY57V56820LT-P
400mil 54pin TSOP II
100MHz
HY57V56820LT-S
LVTTL
133MHz
HY57V56820LT-8
4Banks x 4Mbits
x16
100MHz
Package
100MHz
HY57V56820T-S
Interface
133MHz
HY57V56820T-8
Organization
133MHz
HY57V56820T-H
Power
100MHz
Normal
Lower
Power
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.8/Nov. 01
