SN74AVC245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES263C – APRIL 1999 – REVISED FEBRUARY 2000
D
D
D
D
D
DOC ™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V VCC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ™)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This octal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V
VCC operation.
The SN74AVC245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright © 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
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