ACPL-W611/ACPL-P611
High CMR, High Speed TTL Compatible Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-W611/ACPL-P611 is an optically coupled gate
that combines a GaAsP light emitting diode and an integrated high gain photo detector. The output of the detector IC is an open collector Schottky clamped transistor. The internal shield provides a guaranteed common
mode transient immunity specification of 10,000 V/μs for
the ACPL-W611.
10 kV/μs minimum Common Mode Rejection (CMR)
at VCM = 1000 V
This unique design provides maximum ac and dc circuit
isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to +85°C allowing trouble-free system
performance.
The ACPL-W611/ACPL-P611 is suitable for high speed
logic interfacing, input/output buffering, as line
receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments.
High speed: 10 MBd typical
LSTTL/TTL compatible
Low input current capability: 5 mA
Guaranteed ac and dc performance over temperature:
-40°C to +85°C
Stretched SO-6 package
Safety Approval:
– UL Recognized:
5000Vrms for 1 minute for ACPL-W611 and ACPLP611-020E per UL1577
– CSA
– IEC/EN/DIN EN 60747-5-2
Applications
Functional Diagram
Isolated line receiver
ACPL-W611/ACPL-P611
Computer-peripheral interfaces
1
6
V CC
2
ANODE
5
VO
4
GND
Microprocessor system interfaces
Digital isolation for A/D, D/A conversion
Switching power supply
CATHODE
3
SHIELD
Instrument input/output isolation
Ground loop elimination
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
Pulse transformer replacement
Power transistor isolation in motor drives
Isolation of high speed logic systems
A 0.1 μF bypass capacitor must be connected between pins VCC and GND.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
