VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Features
• ANSI X3T11 Compliant Fibre Channel and IEEE
802.3z Compliant Gigabit Ethernet Transceiver
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• Over 2Gb/s Duplex Raw Data Rate
• PECL Rx Signal Detect and Cable Equalization
• Redundant PECL Tx Outputs and Rx Inputs
• Serial Tx-to-Rx and Parallel Rx-to-Tx Internal
Loopback Modes
• 8B/10B Encoder/Decoder, Optional Encoder/
Decoder Bypass Operation
• Clock Multiplier Generates Baud Rate Clock
• “ASIC-FriendlyTM” Timing Options for Transmitter Parallel Input Data
• Automatic Lock-to-Reference
• Elastic Buffer for Chip-to-Chip Cable Deskewing
• Built-In Self Test
• Tx/Rx Rate Matching via IDLE Insertion/Deletion
• 3.3V Supply, 1.0 W
• Compatible with VSC7211, VSC7214 and
VSC7216
• 100-pin, 14mm TQFP package
• JTAG Boundary Scan Support for TTL I/O
General Description
The VSC7212 is an 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth
interconnection between busses, backplanes, or other subsystems. A Fibre Channel and Gigabit Ethernet
compliant transceiver provides up to 2.18Gb/s of duplex raw data transfer. The VSC7212 can operate at a
maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at 98MHz).
The VSC7212 contains an 8B/10B encoder, serializer, de-serializer, 8B/10B decoder and elastic buffer which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as a non-encoded 10-bit transceiver with redundant I/O.
VSC7212 Block Diagram
RECEIVER
TRANSMITTER
PTXEN
T(7:0)
C/D
WSEN
8
8
8B/10B 10
Encode
D Q
KCHAR
DUAL
TBC
REFCLKP
REFCLKN
G52268-0, Rev 3.3
04/10/01
LBEN(1:0)
RXP/R
LBTX
PTX+
PTXRTX+
RTX-
PRX+
PRXRRX+
RRX-
PSDET
RSDET
RTXEN
x20/x10
Clock Gen
CAP0 CAP1
Clk/Data
Recovery
10
8B/10B
Decode
8
3
8
Elastic
Buffer
WSI
FLOCK
Channel
Align
TRSTN
TMS
TDI
TCK
JTAG
Boundary
Scan
R(7:0)
IDLE
KCH
ERR
RCLK
RCLKN
WSO
Tx Clock
REFCLK
TBERR
REFOUT
TMODE(2:0)
RMODE(1:0)
RESETN
ENDEC
BIST
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
TDO
Page 1
