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ispLSI 1032E
®
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
D7 D6 D5 D4 D3 D2 D1 D0
C7
A0
— High Speed Global Interconnect
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
A2
A3
D Q
A5
C4
C2
C1
A6
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
— Electrically Erasable and Reprogrammable
C0
CLK
EW
Output Routing Pool
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
0139A(A1)-isp
N
Description
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
R
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-volatile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
FO
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
03
2E
A
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
GLB
D
— TTL Compatible Inputs and Outputs
D Q
C3
A4
A7
C5
D Q
Logic
Array
Output Routing Pool
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
C6
ES
IG
N
Output Routing Pool
D Q
A1
S
— 192 Registers
— Four Dedicated Clock Input Pins
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
I1
— Synchronous and Asynchronous Clocks
pL
S
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
SE
is
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032e_09
1
August 2006
