FLEX 6000
Programmable Logic
Device Family
®
March 2001, ver. 4.1
Features...
Data Sheet
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Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes
during prototyping or design testing
Product features
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Register-rich, look-up table- (LUT-) based architecture
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OptiFLEX® architecture that increases device area efficiency
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Typical gates ranging from 5,000 to 24,000 gates (see Table 1)
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Built-in low-skew clock distribution tree
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100% functional testing of all devices; test vectors or scan chains
are not required
System-level features
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In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
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5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
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Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
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MultiVoltTM I/O interface operation, allowing a device to bridge
between systems operating at different voltages
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Low power consumption (typical specification less than 0.5 mA
in standby mode)
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3.3-V devices support hot-socketing
Table 1. FLEX 6000 Device Features
Feature
Typical gates (1)
EPF6010A
EPF6016
EPF6016A
EPF6024A
10,000
16,000
16,000
24,000
Logic elements (LEs)
880
1,320
1,320
1,960
Maximum I/O pins
102
204
171
218
3.3 V
5.0 V
3.3 V
3.3 V
Supply voltage (VCCINT)
Note:
(1)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
Altera Corporation
A-DS-F6000-04.1
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