PRELIMINARY
ICS854104
LOW SKEW, 1-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS854104 is a low skew, high performance
IC
S
1-to-4 Differential-to-LVDS Clock Fanout Buffer
HiPerClockS™ and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the
ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω.
The ICS854104 accepts a differential input level and translates it to LVDS output levels.
• Four LVDS outputs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Each output has an individual OE control
• Maximum output frequency: 700MHz
• Translates differential input signals to LVDS levels
Guaranteed output and part-to-part skew characteristics make
the ICS854104 ideal for those applications demanding well
defined performance and repeatability.
• Additive phase jitter, RMS: 0.1ps (typical)
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 1.1ns (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
OE0
OE1
OE2
VDD
GND
CLK
nCLK
OE3
nQ0
Pullup
OE0
Q1
nQ1
CLK Pulldown
Pullup
OE1
nCLK Pullup/Pulldown
16
15
14
13
12
11
10
9
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
ICS854104
Q2
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
nQ2
Pullup
1
2
3
4
5
6
7
8
OE2
Q3
nQ3
Pullup
OE3
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
1
ICS854104AG REV. A JANUARY 3, 2007
