DATA SHEET
256M bits SDRAM
EDS2516APTA (16M words × 16 bits)
Description
Pin Configurations
The EDS2516AP is a 256M bits SDRAM organized as
4,194,304 words × 16 bits × 4 banks. All inputs and
outputs are referred to the rising edge of the clock
input. It is packaged in standard 54-pin plastic TSOP
(II)
/xxx indicates active low signal.
54-pin plastic TSOP (II)
EO
VDD
DQ0
VDDQ
DQ1
DQ2
Features
•
•
•
•
•
•
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
L
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
LVTTL interface
Single pulsed /RAS
×16 organization
4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
⎯ Sequential (BL = 1, 2, 4, 8, full page)
⎯ Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
• 2 types of TSOP (II) package
⎯ Sn-Pb solder
⎯ Lead free solder (Sn-Bi)
Pr
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A12,
BA0, BA1
od
Address input
Bank select address
DQ0 to DQ15 Data-input/output
Chip select
/CS
Row address strobe
/RAS
Column address strobe
/CAS
Write enable
/WE
UDQM,LDQM Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
t
uc
Document No. E0359E20 (Ver. 2.0)
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003-2005
