DATA SHEET
256M bits SDRAM
EDS2532AABJ-75 (8M words × 32 bits)
Pin Configurations
• Density: 256M bits
• Organization
⎯ 2M words × 32 bits × 4 banks
• Package: 90-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 133MHz (max.)
• 2KB page size
⎯ Row address: A0 to A11
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
/xxx indicates active low signal.
L
EO
Specifications
90-ball FBGA
1
2
3
4
5
6
8
9
A
DQ26 DQ24 VSS
VDD DQ23 DQ21
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
B
C
D
E
VDDQ DQ31
NC
NC
DQ16 VSSQ
VSS DQM3
A3
A2
DQM2 VDD
F
G
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
/CS
/RAS
NC
NC
/CAS
/WE DQM0
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
H
J
K
Pr
DQM1
L
VDDQ DQ8
M
N
P
VDDQ VSSQ DQ4
od
DQ11 VDDQ VSSQ
Features
7
R
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
DQ13 DQ15 VSS
VDD
DQ0
DQ2
(Top view)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
t
uc
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Document No. E0508E40 (Ver. 4.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2004-2005
