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MAT02EHZ

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仕様・特性

a Low Noise, Matched Dual Monolithic Transistor MAT02 PIN CONNECTION FEATURES Low Offset Voltage: 50 ␮V max Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max High Gain (hFE): 500 min at IC = 1 mA 300 min at IC = 1 ␮A Excellent Log Conformance: rBE Ӎ 0.3 ⍀ Low Offset Voltage Drift: 0.1 ␮V/؇C max Improved Direct Replacement for LM194/394 TE TO-78 (H Suffix) PRODUCT DESCRIPTION LE NOTE Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated. SO The design of the MAT02 series of NPN dual monolithic transistors is optimized for very low noise, low drift and low rBE. Precision Monolithics’ exclusive Silicon Nitride “TriplePassivation” process stabilizes the critical device parameters over wide ranges of temperature and elapsed time. Also, the high current gain (hFE) of the MAT02 is maintained over a wide range of collector current. Exceptional characteristics of the MAT02 include offset voltage of 50 µV max (A/E grades) and 150 µV max F grade. Device performance is specified over the full military temperature range as well as at 25°C. The MAT02 should be used in any application where low noise is a priority. The MAT02 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT02. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The MAT02 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1 µA to 10 mA. For applications requiring multiple devices see MAT04 Quad Matched Transistor data sheet. OB Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isolation between the transistors. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

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