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部品型式

AD5340BRUZ

製品説明
仕様・特性

2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Low power parallel data interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input. The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP). 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM VREF VDD 3 12 POWER-ON RESET AD5330 BUF 1 INPUT REGISTER DB7 20 . . DB0 13 CS 6 WR 7 CLR 9 INTERFACE LOGIC GAIN 8 DAC REGISTER 8-BIT DAC RESET BUFFER 4 VOUT POWER-DOWN LOGIC 11 5 PD GND 06852-001 LDAC 10 Figure 1. AD5330 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.

ブランド

AD

会社名

Analog Devices

本社国名

U.S.A

事業概要

半導体デバイスを製造するアメリカの多国籍企業。特にADC、DAC、MEMS、DSPなどに強い。現在は 65nm から 3μm のプロセスルールの回路を設計している。

供給状況

 
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