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ST313021A
STA5620 Fully integrated RF front-end receiver for GPS applications Features ■ Low IF architecture (fIF = 4fO) ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7 V supply voltage ■ SPI interface ■ 2 kV HBM ESD protected ■ Compatible with GPS L1 ■ Standard QFN-32 package ■ Low power for portable designs du o VFQFPN32 Pr e let o The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength. Description )(s The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42 MHz to 4.092 MHz. ct u The IF signal is converted by a two bit ADC. Sign (SIGN), Magnitude (MAG) and the 16.368 MHz sampling clock (GPS_CLK) are provided to the baseband. od r P e let o Table 1. bs O (s) ct bs O An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver. The on-chip oscillator supports crystal frequencies in the range of 10MHz to 40MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency. The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package. Device summary Order code Marking Package Packing STA5620TR STA5620 VFQFPN32 Tape & reel February 2008 Rev 4 1/29 www.st.com 1
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