Features
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead
SAP and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
Two-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ
SOIC, 8-lead MAP (24C128), 8-lead TSSOP, 8-lead SOIC Array Package and 8-ball
dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and
1.8V (1.8V to 3.6V) versions.
Pin Name
Function
A0 - A1
Address Inputs
SDA
Serial Data
SCL
Write Protect
A0
A1
NC
GND
1
2
3
4
8
7
6
5
128K (16,384 x 8)
256K (32,768 x 8)
AT24C128(1)
AT24C256(2)
Notes:
1. Not recommended for
new design; please
refer to AT24C128B
datasheet.
2. Not recommended for
new design; please
refer to AT24C256B
datasheet.
VCC
WP
SCL
SDA
Serial Clock Input
WP
8-lead TSSOP
8-lead PDIP
Table 1. Pin Configuration
Two-wire Serial
EEPROMs
NC
No Connect
GND
Ground
A0
A1
NC
GND
8
7
6
5
1
2
3
4
VCC
WP
SCL
SDA
8-lead SOIC
A0
A1
NC
GND
1
2
3
4
8
7
6
5
8-lead MAP
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
NC
GND
Bottom View
8-ball dBGA2
VCC
WP
SCL
SDA
8
1
7
2
6
3
5
4
A0
A1
NC
GND
Bottom View
8-lead SAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
NC
GND
Bottom View
0670T–SEEPR–3/07
1
AT24C128/256
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24CXX devices. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive
coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive
coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the pin to GND.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.
3
0670T–SEEPR–3/07
