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GAL20XV10B-20LP

製品説明
仕様・特性

GAL20XV10 Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology I/CLK 4 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q I 4 • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 90mA Maximum Icc — 75mA Typical Icc I • ACTIVE PULL-UPS ON ALL PINS I • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100 ms) — 20 Year Data Retention PROGRAMMABLE AND-ARRAY (40 X 40) 4 I I I • TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4 — Registered or Combinatorial with Polarity I I • PRELOAD AND POWER-ON RESET OF ALL REGISTERS • APPLICATIONS INCLUDE: — High Speed Counters — Graphics Processing — Comparators 4 4 4 4 4 I 4 I 4 • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description I/OE The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. Pin Configuration DIP PLCC The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL® architectures listed in the macrocell description section of this document. The GAL20XV10 is capable of emulating these PAL architectures with full function and parametric compatibility. 4 I 2 I/O/Q 25 NC I GAL20XV10 Top View 23 I I/O/Q I/O/Q I/O/Q 6 18 I/O/Q I/O/Q I I/O/Q 9 I I/O/Q 18 I I/O/Q I I/O/Q 21 19 11 I/OE I/O/Q 16 NC I I GND 14 12 Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I I/O/Q NC I I I/O/Q GAL 20XV10 I/O/Q 7 I/O/Q Vcc I/O/Q I I/O/Q 5 I I 24 I 26 28 1 I I/O/Q Vcc I/CLK NC I I I/CLK I/O/Q I GND I/O/Q 12 13 I/OE Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm High-Speed E2CMOS PLD Generic Array Logic™ Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 20xv10_02 1 July 1997 Specifications GAL20XV10 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Output Logic Macrocell (OLMC) Exclusive-OR macrocells. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array. The following discussion pertains to configuring the Output Logic Macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. The GAL20XV10 has two global architecture configurations that allow it to emulate PAL architectures. The Input mode emulates combinatorial PAL devices, with the I/CLK and I/OE pins used as inputs. The Feedback mode emulates registered PAL devices with the I/CLK pin used as the register clock and the I/OE pin as an output enable for all registers. The following is a list of PAL architectures that the GAL20XV10 can emulate. It also shows the global architecture mode used to emulate the PAL architecture. PAL Architectures Emulated by GAL20XV10 PAL12L10 PAL20L10 PAL20X10 PAL20X8 PAL20X4 REGISTERED CONFIGURATION The Macrocell is set to Registered configuration when AC0 = 1 and AC1 = 0. Three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high transition of the I/CLK. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array. GAL20XV10 Global OLMC Mode Input Mode Input Mode Feedback Mode Feedback Mode Feedback Mode XOR COMBINATORIAL CONFIGURATION The Macrocell is set to the Exclusive-OR Combinatorial configuration when AC0 = 0 and AC1 = 1. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed to an output buffer. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable that is common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buffer path on macrocells 2 through 9 only, macrocells 1 and 10 have no input into the AND array. INPUT MODE The Input mode architecture is defined when the global architecture bit SYN = 1. In this mode, the I/CLK pin becomes an input to the AND array and also provides the clock source for all registers. The I/OE pin becomes an input into the AND array and provides the output enable control for any macrocell configured as an Exclusive-OR function. Feedback into the AND array is provided from macrocells 2 through 9 only. In this mode, macrocells 1 and 10 have no feedback into the AND array. FEEDBACK MODE The Feedback mode architecture is defined when the global architecture bit SYN = 0. In this mode the I/CLK pin becomes a dedicated clock source for all registers. The I/OE pin is a dedicated output enable control for any macrocell configured as an Exclusive-OR function. The I/CLK and I/OE pins are not available to the AND array in this mode. Feedback into the AND array is provided on all macrocells 1 through 10. COMBINATORIAL CONFIGURATION The Macrocell is set to Combinatorial mode when AC0 = 1 and AC1 = 1. Three of the four product terms are used as sum-ofproduct terms for the combinatorial output. The XOR bit controls the polarity of the output. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buffer path on macrocells 2 through 9 only, macrocells 1 and 10 have no input into the AND array. FEATURES Each Output Logic Macrocell has four possible logic function configurations controlled by architecture control bits AC0 and AC1. Four product terms are fed into each macrocell. XOR REGISTERED CONFIGURATION The Macrocell is set to the Exclusive-OR Registered configuration when AC0 = 0 and AC1 = 0. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed into a D-type register. The register is clocked by the low-to-high transition of the I/CLK pin. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable common to all 3

ブランド

LATTICE

会社名

Lattice Semiconductor Corporation

本社国名

U.S.A

事業概要

主力製品は、FPGA(Field-Programmable Gate Array)、CPLD(Complex Programmable Logic Device)、プログラマブルパワーマネジメント製品である。 FPGAの世界シェアはザイリンクス、アルテラに次いで第3位である。 半導体ベンダーのため、自社で生産ラインは保有していない。製造は富士通セミコンダクターなどで行っている。

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GAL20XV10B-20LPの取扱い販売会社 株式会社クレバーテック  会社情報(PDF)    戻る

ca 0001506150000  0122308060000  0122310020000  0082312150000  0102401010000 

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GAL2048B25QP GAL208VA-25LP GAL20C8A-10CP GAL20L8-102JC GAL20L8VS-15HB1
GAL20LV82D-25QJ GAL20LV8D-3LJ GAL20LV8D-7LJ GAL20LV8D-7LJ28 GAL20LV8D-7LJN
GAL20LV8ZD15QJ GAL20LV8ZD-25QJ GAL20R10-15LP GAL20R10B15LP GAL20RA10
GAL20RA10-12LJ GAL20RA10-12LP GAL20RA10-15LJ GAL20RA10-15LJ-LAT GAL20RA10-15LP
GAL20RA10-15LVC GAL20RA10-20LD883C GAL20RA10-20LJ GAL20RA10-20LP GAL20RA10-25NC
GAL20RA1030LJ GAL20RA10-30LP GAL20RA10B GAL20RA10B-10LJ GAL20RA10B-10LJN
GAL20RA10B-10LP GAL20RA10B-10LPN GAL20RA10B-15LJ GAL20RA10B-15LJN GAL20RA10B-15LP
GAL20RA10B-15LPN GAL20RA10B-20LJ GAL20RA10B-20LJI GAL20RA10B-20LP GAL20RA10B-20LPI
GAL20RA10B-20LPN GAL20RA10B-20LP-PROGRAM GAL20RA10B-30LP GAL20RA10B-7LJ GAL20RA10L15LJ
GAL20V10B-10LP GAL20V-10LP GAL20V10Q-25PC4 GAL20V12LP GAL20V8
GAL20V8010LP GAL20V80B-15QP GAL20V8-10LJ GAL20V8-10LMC GAL20V8-10LNC
GAL20V8-10LP GAL20V8-10LVC GAL20V8-12LP GAL20V8-15 GAL20V8-15CH1
GAL20V8-15HB1 GAL20V8-15HBJ GAL20V8-15HC1 GAL20V8-15HCI GAL20V8-15LJ
GAL20V815LJRT GAL20V815LJS GAL20V815LNC GAL20V8-15LP GAL20V8-15LPS
GAL20V815P GAL20V8-20HB1 GAL20V8-20HC1 GAL20V820L GAL20V8-20LJ
GAL20V8-20LNC GAL20V8-20LNCTI GAL20V8-20LP GAL20V8-20LVC GAL20V8-20QP
GAL20V8-25 GAL20V8-25CP GAL20V8-25HB1 GAL20V8-25HB1STDIP GAL20V8-25HC1
GAL20V8-25HCI GAL20V8-25HCT GAL20V825LB GAL20V8-25LJ GAL20V825LJPP
GAL20V8-25LN GAL20V8-25LNC GAL20V8-25LNCNSC GAL20V8-25LNCWIPED GAL20V8-25LP
GAL20V825LPI GAL20V8-25LPN GAL20V8-25LVC GAL20V8-25P GAL20V8-25QB1
GAL20V8-25QJ GAL20V8-25QJI GAL20V8-25QL GAL20V8-25QNC GAL20V8-25QP
GAL20V8-25QPI GAL20V8-25QVC GAL20V8-30LCM GAL20V8-35LP GAL20V835QNC
GAL20V8-35QP GAL20V8-35QPI GAL20V84-10LP GAL20V8-7LG GAL20V88-15LJ
GAL20V8A GAL20V8A10HB GAL20V8A-10JL GAL20V8A-10LJ GAL20V8A-10LJC
GAL20V8A-10LP GAL20V8A-10LP-LAT9 GAL20V8A-10LP-PULLS GAL20V8A-10LP-SP GAL20V8A-10LVC
GAL20V8A-12 GAL20V8A-12LJ GAL20V8A-12LNC GAL20V8A12LNP GAL20V8A-12LP
GAL20V8A-12LVC GAL20V8A-12NC GAL20V8A-15J GAL20V8A-15JC GAL20V8A-15JL
GAL20V8A-15JVC GAL20V8A-15L GAL20V8A-15LC GAL20V8A-15LD GAL20V8A15LD883
GAL20V8A-15LD883C GAL20V8A-15LDI GAL20V8A-15LI GAL20V8A-15LJ GAL20V8A15LJC
GAL20V8A15LJN GAL20V8A-15LJPROG GAL20V8A-15LJ-PULLS GAL20V8A-15LJUSED GAL20V8A15LN
GAL20V8A-15LNC GAL20V8A-15LNC322 GAL20V8A-15LNC-PULLS GAL20V8A-15LNE GAL20V8A15LNI
GAL20V8A-15LP GAL20V8A-15LPLATTIC GAL20V8A15LPN GAL20V8A-15LP-PULLS GAL20V8A-15LV1
GAL20V8A-15LVC GAL20V8A-15LVI GAL20V8A-15NC GAL20V8A-15NL GAL20V8A-15QJ
GAL20V8A15QJLJ GAL20V8A15QP GAL20V8A-15UVC GAL20V8A-1OLP GAL20V8A-1SLP
GAL20V8A-20LCM GAL20V8A-20LD GAL20V8A-20LD883C GAL20V8A-20LDM GAL20V8A20LJ
GAL20V8A-20LJI GAL20V8A-20LP GAL20V8A20LPN GAL20V8A20QP GAL20V8A-25
GAL20V8A-250J GAL20V8A-25LJ GAL20V8A-25LP GAL20V8A-25LPI GAL20V8A-25LP-LAT8
GAL20V8A-25LPN GAL20V8A25LPPULLS GAL20V8A-25P GAL20V8A-25Q GAL20V8A-25QD883C
GAL20V8A-25QJ GAL20V8A-25QJI GAL20V8A-25QJ-LAT9 GAL20V8A-25QP GAL20V8A-25QP9140
GAL20V8A25QP92+ GAL20V8A25QPI GAL20V8A-30LCM GAL20V8A-30LD883C GAL20V8A-7LJ
GAL20V8A-7LP GAL20V8A-A5LP GAL20V8A-L25LJ GAL20V8A-LJ GAL20V8AS-10
GAL20V8AS-10HB1 GAL20V8AS-10HBI GAL20V8AS-10HC1 GAL20V8AS-10HCI GAL20V8AS12HB1
GAL20V8AS-12HBI GAL20V8AS12HC1J GAL20V8AS-15B1 GAL20V8AS-15HB1 GAL20V8AS-15HB1-PULLS
GAL20V8AS-15HBI GAL20V8AS-15HC1 GAL20V8AS15HC1J GAL20V8AS-15QB1 GAL20V8AS20HB1
GAL20V8AS-20HCIJ GAL20V8AS25HB1 GAL20V8AS-25HC1J GAL20V8AS-25QB1 GAL20V8B
GAL20V8B-10 GAL20V8B-10JI GAL20V8B-10LD GAL20V8B-10LD883 GAL20V8B-10LJ
GAL20V8B-10LJI GAL20V8B-10LJ-LAT9 GAL20V8B-10LJU GAL20V8B-10LP GAL20V8B10LP9293
GAL20V8B-10LPI GAL20V8B-10LP-LAT9 GAL20V8B-10LPN GAL20V8B-10LPNI GAL20V8B-10LPPROGRAMMED
GAL20V8B-10LR883 GAL20V8B12LJ GAL20V8B-12LP GAL20V8B-14LP GAL20V8B-150J
GAL20V8B-15JC GAL20V8B-15JC4 GAL20V8B-15JI GAL20V8B-15L GAL20V8B15LD
GAL20V8B-15LD883 GAL20V8B15LD883D GAL20V8B-15LJ GAL20V8B-15LJ28 GAL20V8B-15LJI
GAL20V8B-15LJN GAL20V8B-15LJNI GAL20V8B-15LJPROG GAL20V8B-15LJ-PULLS GAL20V8B-15LP
GAL20V8B-15LP24 GAL20V8B-15LPGAL20V8B GAL20V8B-15LPI GAL20V8B-15LPN GAL20V8B-15LPNI
GAL20V8B-15LPSOFTVERS GAL20V8B-15LPUSED GAL20V8B-15QJ GAL20V8B-15QJN GAL20V8B-15QP
GAL20V8B-15QPI GAL20V8B-15QPN GAL20V8B-20LD883 GAL20V8B-20LD883C GAL20V8B-20LJ
GAL20V8B-20PQI GAL20V8B-20QJI GAL20V8B-20QJNI GAL20V8B-20QP GAL20V8B-20QPI
GAL20V8B-20QPNI GAL20V8B-250J GAL20V8B-250QJ GAL20V8B-25CP GAL20V8B-25JC
GAL20V8B-25JL GAL20V8B-25L GAL20V8B-25LB GAL20V8B-25LJ GAL20V8B-25LJI
GAL20V8B-25LJN GAL20V8B-25LP GAL20V8B-25LP24 GAL20V8B25LPI GAL20V8B-25LPLATTIC
GAL20V8B-25LPN GAL20V8B-25LPNI GAL20V8B-25QJ GAL20V8B-25QJI GAL20V8B-25QJN

0.0792789459