GAL20XV10
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
I/CLK
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OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
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• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 90mA Maximum Icc
— 75mA Typical Icc
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• ACTIVE PULL-UPS ON ALL PINS
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• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
PROGRAMMABLE
AND-ARRAY
(40 X 40)
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• TEN OUTPUT LOGIC MACROCELLS
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
— Registered or Combinatorial with Polarity
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• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
— High Speed Counters
— Graphics Processing
— Comparators
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• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
I/OE
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently.
Pin Configuration
DIP
PLCC
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL® architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
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2
I/O/Q
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NC
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GAL20XV10
Top View
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I/O/Q
I/O/Q
I/O/Q
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18
I/O/Q
I/O/Q
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I/O/Q
9
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I/O/Q
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I/O/Q
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I/O/Q
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I/OE
I/O/Q
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NC
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GND
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Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
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I/O/Q
NC
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I/O/Q
GAL
20XV10
I/O/Q
7
I/O/Q
Vcc
I/O/Q
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I/O/Q
5
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24
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26
28
1
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I/O/Q
Vcc
I/CLK
NC
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I/CLK
I/O/Q
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GND
I/O/Q
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I/OE
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
High-Speed E2CMOS PLD
Generic Array Logic™
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20xv10_02
1
July 1997
Specifications GAL20XV10
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Output Logic Macrocell (OLMC)
Exclusive-OR macrocells. In Feedback mode, the state of the
register is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the register
is available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback
into the AND array.
The following discussion pertains to configuring the Output Logic
Macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.
The GAL20XV10 has two global architecture configurations that
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/CLK and I/OE pins used as
inputs. The Feedback mode emulates registered PAL devices with
the I/CLK pin used as the register clock and the I/OE pin as an
output enable for all registers. The following is a list of PAL architectures that the GAL20XV10 can emulate. It also shows the
global architecture mode used to emulate the PAL architecture.
PAL Architectures Emulated by
GAL20XV10
PAL12L10
PAL20L10
PAL20X10
PAL20X8
PAL20X4
REGISTERED CONFIGURATION
The Macrocell is set to Registered configuration when AC0 = 1 and
AC1 = 0. Three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting output
buffer is enabled by the fourth product term. The output is enabled while this product term is true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high transition of the I/CLK. In Feedback mode, the state of the register
is available to the AND array via an internal feedback path on
all macrocells. In Input mode, the state of the register is available
to the AND array via an internal feedback path on macrocells
2 through 9 only, macrocells 1 and 10 have no feedback into the
AND array.
GAL20XV10 Global
OLMC Mode
Input Mode
Input Mode
Feedback Mode
Feedback Mode
Feedback Mode
XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configuration when AC0 = 0 and AC1 = 1. The four product terms are segmented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed to an output
buffer. The inverting output buffer is enabled by the I/OE pin,
which is an active low output enable that is common to all XOR
macrocells. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available to
the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
INPUT MODE
The Input mode architecture is defined when the global
architecture bit SYN = 1. In this mode, the I/CLK pin becomes an
input to the AND array and also provides the clock source for
all registers. The I/OE pin becomes an input into the AND array
and provides the output enable control for any macrocell configured as an Exclusive-OR function. Feedback into the AND array
is provided from macrocells 2 through 9 only. In this mode,
macrocells 1 and 10 have no feedback into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global
architecture bit SYN = 0. In this mode the I/CLK pin becomes a
dedicated clock source for all registers. The I/OE pin is a dedicated output enable control for any macrocell configured as an
Exclusive-OR function. The I/CLK and I/OE pins are not available to the AND array in this mode. Feedback into the AND array
is provided on all macrocells 1 through 10.
COMBINATORIAL CONFIGURATION
The Macrocell is set to Combinatorial mode when AC0 = 1 and
AC1 = 1. Three of the four product terms are used as sum-ofproduct terms for the combinatorial output. The XOR bit controls
the polarity of the output. The inverting output buffer is enabled
by the fourth product term. The output is enabled while this product
term is true. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available
to the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
FEATURES
Each Output Logic Macrocell has four possible logic function
configurations controlled by architecture control bits AC0 and AC1.
Four product terms are fed into each macrocell.
XOR REGISTERED CONFIGURATION
The Macrocell is set to the Exclusive-OR Registered configuration
when AC0 = 0 and AC1 = 0. The four product terms are segmented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a D-type
register. The register is clocked by the low-to-high transition of the
I/CLK pin. The inverting output buffer is enabled by the
I/OE pin, which is an active low output enable common to all
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