MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
•
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC1455xBCP
AWLYYWWG
1
1
Features
•
•
•
•
•
•
http://onsemi.com
Diode Protection on All Inputs
Active High or Active Low Outputs
Expandable
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
1
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
16
1455xBG
AWLYWW
1
16
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
x
A
WL, L
YY, Y
WW, W
G
MC1455xB
ALYWG
1
= 5 or 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Symbol
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
± 10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
EA
1
16
VDD
EA
1
16
VDD
Lead Temperature (8−Second Soldering)
TL
260
°C
AA
2
15
EB
AA
2
15
EB
BA
3
14
AB
BA
3
14
AB
Q0A
4
13
BB
Q0A
4
13
BB
Q1A
5
12
Q0B
Q1A
5
12
Q0B
Q2A
6
11
Q1B
Q2A
6
11
Q1B
Q3A
7
10
Q2B
Q3A
7
10
Q2B
VSS
8
9
Q3B
VSS
8
9
Q3B
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
PIN ASSIGNMENTS
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
MC14555B
MC14556B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 9
1
Publication Order Number:
MC14555B/D
MC14555B, MC14556B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C)
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Typ
(Note 6)
Max
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
220
95
70
440
190
140
5.0
10
15
−
−
−
200
85
65
400
170
130
tPLH,
tPHL
Propagation Delay Time − E to Output
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
Min
tTLH,
tTHL
Propagation Delay Time − A, B to Output
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
VDD
5.0
10
15
Symbol
tPLH,
tPHL
Unit
ns
ns
ns
5. The formulas given are for the typical characteristics only at 25°C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
20 ns
INPUT A HIGH, INPUT E LOW
20 ns
20 ns
A INPUTS
(50% DUTY CYCLE)
1
2f
90%
50%
10%
VDD
VSS
VDD
tPHL
VOH
OUTPUT Q1
VDD
90%
50%
10%
INPUT B
VSS
B INPUTS
(50% DUTY CYCLE)
20 ns
VOL
All 8 outputs connect to respective CL loads.
f in respect to a system clock.
90%
50%
10%
OUTPUT Q3
MC14556B
tTHL
tPLH
OUTPUT Q3
MC14555B
Q0
A
*
Q1
B
*
Q2
*
Q3
E
3
VOH
VOL
Figure 2. Dynamic Signal Waveforms
*
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V
tTLH OL
tTHL
LOGIC DIAGRAM
(1/2 of Dual)
*Eliminated for MC14555B
VOH
tPHL
90%
50%
10%
tTLH
Figure 1. Dynamic Power Dissipation Signal Waveforms
VSS
tPLH
