March 1996
NDC7002N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
0.51A, 50V, RDS(ON) = 2Ω @ VGS=10V
These dual N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. These devices is
particularly suited for low voltage applications requiring a
low current high side switch.
High density cell design for low RDS(ON).
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
____________________________________________________________________________________________
4
3
5
2
6
1
SOT-6 (SuperSOTTM-6)
Absolute Maximum Ratings T A = 25°C unless otherwise noted
Symbol
Parameter
NDC7002N
Units
VDSS
VGSS
Drain-Source Voltage
50
V
Gate-Source Voltage - Continuous
20
V
ID
Drain Current - Continuous
(Note 1a)
0.51
A
PD
Maximum Power Dissipation
(Note 1a)
0.96
- Pulsed
1.5
(Note 1b)
TJ,TSTG
0.9
(Note 1c)
W
0.7
Operating and Storage Temperature Range
-55 to 150
°C
(Note 1a)
130
°C/W
(Note 1)
60
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
© 1997 Fairchild Semiconductor Corporation
NDC7002N.SAM
