Datasheet
Serial EEPROM series Standard EEPROM
I2C BUS EEPROM (2-Wire)
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
●General Description
2
BR24Sxxx-W is a serial EEPROM of I C BUS interface method
●Packages W(Typ.) x D(Typ.) x H(Max.)
●Features
2
Completely conforming to the world standard I C
BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
1.7V to 5.5V single power source action most suitable
for battery use
FAST MODE 400kHz at 1.7V to 5.5V
Page write mode useful for initial value write at
factory shipment
Highly reliable connection by Au pad and Au wire
Auto erase and auto end function at data rewrite
Low current consumption
At write operation (5V)
: 0.5mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
Data rewrite up to 1,000,000 times
Data kept for 40 years
Noise filter built in SCL / SDA terminal
Shipment data all address FFh
SOP8
TSSOP-B8
5.00mm x 6.20mm x 1.71mm
3.00mm x 6.40mm x 1.20mm
SOP- J8
TSSOP-B8J
4.90mm x 6.00mm x 1.65mm
3.00mm x 4.90mm x 1.10mm
SSOP-B8
MSOP8
3.00mm x 6.40mm x 1.35mm
2.90mm x 4.00mm x 0.90mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
●Page write
Number of pages
16Byte
64Byte
BR24S08-W
BR24S16-W
Product number
32Byte
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
●BR24Sxxx-W
Capacity
Bit
format
Type
Power source
voltage
SOP8
SOP-J8
8Kbit
1K×8
BR24S08-W
1.7V to 5.5V
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16Kbit
2K×8
BR24S16-W
1.7V to 5.5V
●
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32Kbit
4K×8
BR24S32-W
1.7V to 5.5V
●
64Kbit
8K×8
BR24S64-W
1.7V to 5.5V
●
128Kbit
16K×8
BR24S128-W
1.7V to 5.5V
256Kbit
32K×8
BR24S256-W
1.7V to 5.5V
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･14･001
MSOP8
TSSOP-B8J
VSON008
X2030
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SSOP-B8 TSSOP-B8
○This product is not designed protection against radioactive rays
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TSZ02201-0R2R0G100320-1-2
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BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Action timing characteristics
(Unless otherwise specified, Ta=-40℃ to +85℃, VCC=1.7V to 5.5V)
Parameter
Limits
Symbol
SCL Frequency
Data clock "High" time
Data clock "Low" time
SDA, SCL rise time *1
SDA, SCL fall time
*1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition data setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA,SCL terminal)
WP hold time
WP setup time
WP valid time
Min.
0.6
1.2
0.6
0.6
0
100
0.1
0.1
0.6
1.2
0
0.1
1.0
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Typ.
-
Unit
Max.
400
0.3 *2
0.3
0.9
5
0.1
-
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1 : Not 100% TESTED
*2 : BR24S16/64-W : 1.0μs.
●Sync data input / output timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
tHD:STA
tSU:STO
SDA
(入力)
(Input)
SDA
tBUF
tPD
tDH
SDA
(出力)
(Output)
START BIT
STOP BIT
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(b) Start - stop bit timing
SCL
SCL
DATA(1)
SDA
D0
ACK
WRITE DATA(n)
SDA
tWR
STOP
CONDITION
D1
D0
DATA(n)
ACK
ACK
ｔWR
START
CONDITION
ストップコンディション
Stop condition
WP
tSU：WP
Figure 1-(c) Write cycle timing
ｔHD：WP
Figure 1-(d) WP timing at write execution
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
