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74F191
54F 74F191 Up Down Binary Counter with Preset and Ripple Clock General Description Features Commercial Y Y Y Y High-Speed 125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable e The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters In the counting modes state changes are initiated by the rising edge of the clock Package Number Military N16E 16-Lead (0 300 Wide) Molded Dual-In-Line et 74F191PC Package Description 54F191DM (Note 2) 16-Lead Ceramic Dual-In-Line M16A 16-Lead (0 150 Wide) Molded Small Outline JEDEC 74F191SJ (Note 1) M16D 16-Lead (0 300 Wide) Molded Small Outline EIAJ 54F191FM (Note 2) W16A 16-Lead Cerpack 54F191LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier Type C bs ol J16A 74F191SC (Note 1) Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9495–1 O IEEE IEC TL F 9495 – 2 TL F 9495 – 3 TL F 9495–4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9495 RRD-B30M75 Printed in U S A 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock November 1994 et e Logic Diagram TL F 9495 – 5 bs ol Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays TL F 9495 – 6 O FIGURE 1 n-Stage Counter Using Ripple Clock TL F 9495 – 7 FIGURE 2 Synchronous n-Stage Counter Using Ripple Carry Borrow TL F 9495 – 8 FIGURE 3 Synchronous n-Stage Counter with Gated Carry Borrow 3
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