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74F824D
INTEGRATED CIRCUITS 74F821/822/823/824/825/826 Bus interface registers Product specification IC15 Data Handbook Philips Semiconductors 1996 Jan 05 Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS 74F (U.L.) HIGH/LOW DESCRIPTION LOAD VALUE HIGH/LOW Dn Data inputs 1.0/1.0 20µA/0.6mA 74F821 CP Clock input 1.0/1.0 20µA/0.6mA 74F822 OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F823 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F824 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn Data outputs 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F825 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F826 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA 1200/106.7 24mA/64mA Qn, Qn Data outputs Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION – 74F821 OE 1 22 Q1 D2 4 20 Q3 D4 6 17 Q6 D7 9 15 Q8 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D9 11 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 VCC = Pin 24 GND = Pin 12 14 Q9 GND 12 13 1 13 CP SF00482 1996 Jan 05 7 16 Q7 D8 10 6 18 Q5 D6 8 5 19 Q4 D5 7 4 21 Q2 D3 5 3 23 Q0 D1 3 2 24 VCC D0 2 LOGIC SYMBOL – 74F821 3 23 22 21 20 19 18 17 16 15 14 SF00483
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