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74F825D

製品説明
仕様・特性

54F 74F825 8-Bit D-Type Flip-Flop General Description Features The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Y Commercial Package Number Military 74F825SPC Y Y Y TRI-STATE output Clock enable and clear Multiple output enables Direct replacement for AMD’s Am24825 Package Description N24C 24-Lead (0 300 Wide) Ceramic Dual-In-Line M24B 74F825SC (Note 1) 24-Lead (0 300 Wide) Molded Dual-In-Line J24F 54F825SDM (Note 2) 24-Lead (0 300 Wide) Molded Small Outline JEDEC 54F825FM (Note 2) W24C 24-Lead Cerpack 54F825LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9597 – 1 TL F 9597 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9597 RRD-B30M75 Printed in U S A 54F 74F825 8-Bit D-Type Flip-Flop December 1994 Functional Description The ’F825 consists of eight D-type edge-triggered flip-flops This device has TRI-STATE true outputs and is organized in broadside pinning In addition to the clock and output enable pins the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition With the OE LOW the contents of the flip-flops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops The ’F825 has Clear (CLR) and Clock Enable (EN) pins When the CLR is LOW and the OE is LOW the outputs are LOW When CLR is HIGH data can be entered into the flipflops When EN is LOW data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition When the EN is HIGH the outputs do not change state regardless of the data or clock input transitions Function Table Inputs Internal Output OE CLR EN CP D Q O H H H L H L H H L L L L H H H H L L H H H H H H L L H H X X L L L L L L H L X X X X L L L L H L X X X X X X L H L H X X NC NC NC NC H H H L H L NC NC Z Z Z NC Z L Z Z L H NC NC Function Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data L e LOW Voltage Level H e HIGH Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TL F 9597 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3

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