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部品型式

AD807A-155BR

製品説明
仕様・特性

a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery— No Crystal Required Quantizer Sensitivity: 2 mV Level Detect Range: 2.0 mV to 30 mV Single Supply Operation: +5 V or –5.2 V Low Power: 170 mW 10 KH ECL/PECL Compatible Output Package: 16-Lead Narrow 150 mil SOIC The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. PRODUCT DESCRIPTION The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 170 mW and operates from a single power supply at either +5 V or –5.2 V. The PLL has a factory-trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a FUNCTIONAL BLOCK DIAGRAM CF1 CF2 PIN QUANTIZER + COMPENSATING ZERO ⌽DET – NIN ⌺ LOOP FILTER PHASE-LOCKED LOOP VCO THRADJ SIGNAL LEVEL DETECTOR LEVEL DETECT COMPARATOR/ BUFFER CLKOUTP FDET CLKOUTN RETIMING DEVICE + – DATAOUTP DATAOUTN AD807 SDOUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

ブランド

AD

会社名

Analog Devices

本社国名

U.S.A

事業概要

半導体デバイスを製造するアメリカの多国籍企業。特にADC、DAC、MEMS、DSPなどに強い。現在は 65nm から 3μm のプロセスルールの回路を設計している。

供給状況

 
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