a
FEATURES
10 ps Delay Resolution
2.5 ns to 10 s Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation—310 mW
MIL-STD-883 Compliant Versions Available
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High Stability Timing Source
Multiple Phase Clock Generators
Digitally Programmable
Delay Generator
AD9500
FUNCTIONAL BLOCK DIAGRAM
CEXT
TRIGGER
TRIGGER
RESET
ECL COMMON
CS
+VS
AD9500
DIFFERENTIAL
ANALOG
INPUT
STAGE
TIMING
CONTROL
CIRCUIT
Q
RESET
ECLREF
RS
ECL
VOLTAGE
REFERENCE
Q
INTERNAL DAC
QR
REFERENCE
CURRENT
TTL LATCHES
RSET
–VS
The AD9500 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as 10 ps. The AD9500 is constructed in a high performance bipolar process, designed to
provide high speed operation for both digital and analog circuits.
1
24
2
23
D2
D6
3
22
D1
D7 (MSB)
4
21 D 0 (LSB)
ECLREF
6
CS
AD9500
5
OFFSET ADJUST
20
TOP VIEW
(Not to Scale)
LATCH ENABLE
RS
+VS
8
17
–VS
TRIGGER
9
16
ECL COMMON
TRIGGER 10
15
QR
RESET 11
14
Q
RESET 12
13
Q
4
3
D1
18
D2
GROUND
7
D3
19
2
1
28
27
26
D7 (MSB) 5
25 D (LSB)
0
ECLREF 6
24 LATCH ENABLE
AD9500
OFFSET ADJUST 7
NC 8
23 GROUND
22 NC
TOP VIEW
(Not to Scale)
CS 9
21 RS
+VS 10
20 –VS
TRIGGER 11
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
14
15
16
17
RESET
RESET
NC
Q
Q
18
QR
13
TRIGGER
19 ECL COMMON
12
REV. D
LATCH OFFSET
ENABLE ADJUST
D3
D5
D4
The AD9500 is available as an industrial temperature range
device, –25°C to +85°C, and as an extended temperature range
device, –55°C to +125°C. Both grades are packaged in a 24-lead
cerdip (0.3" package width), as well as 28-leaded and leadless
surface mount packages. The AD9500 is available in versions
compliant with MIL-STD-883. Refer to the Analog Devices
Military Products Databook or current AD9500/883B data
sheet for detailed specifications.
D4
NC
The digital control data is passed to the AD9500 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9500 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9500
latches.
(MSB)
PIN CONFIGURATIONS
D6
The AD9500 employs differential TRIGGER and RESET
inputs which are designed primarily for ECL signal levels but
function with analog and TTL input levels. An onboard ECL
reference midpoint allows both of the inputs to be driven by
either single ended or differential ECL circuits. The AD9500
output is a complementary ECL stage, which also provides a Q R
parallel output circuit to facilitate reset timing implementations.
D0 D1 D2 D3 D4 D5 D6 D7
(LSB)
D5
GENERAL DESCRIPTION
GROUND
–VS
NC = NO CONNECT
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Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
