14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual
Serial Output Analog-to-Digital Converter (ADC)
AD9644
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD9644
VIN+A
VIN–A
PIPELINE
14-BIT ADC
14
VCMA
VIN+B
VIN–B
PIPELINE
14-BIT ADC
14
VCMB
REFERENCE
PDWN
SERIAL PORT
(SPI)
SCLK SDIO CSB
DRGND
DOUT+A
DOUT–A
DSYNC+A
DSYNC–A
DOUT+B
DOUT–B
DSYNC+B
DSYNC–B
PLL
1 TO 8
CLOCK
DIVIDER
CLK+ CLK– SYNC
09180-001
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz and 80 MSPS
SNR = 71.7 dBFS at 70 MHz and 155 MSPS
SFDR = 92 dBc at 70 MHz and 80 MSPS
SFDR = 92 dBc at 70 MHz and 155 MSPS
Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
JESD204A 8-BIT/10-BIT
CODING, SERIALIZER AND
CML DRIVERS
FEATURES
Figure 1. 48-Lead 7 mm × 7 mm LFCSP
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
An on-chip PLL allows users to provide a single ADC
sampling clock; the PLL multiplies the ADC sampling
clock to produce the corresponding JESD204A data rate
clock.
The configurable JESD204A output block supports up to
1.6 Gbps per channel data rate when using a dedicated
data link per ADC or 3.2 Gbps data rate when using a
single shared data link for both ADCs.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 250 MHz.
Operation from a single 1.8 V power supply.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding),
controlling the clock DCS, power-down, test modes,
voltage reference mode, and serial output configuration.
Rev. C
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