Complete 14-Bit
CCD/CIS Signal Processor
AD9822
FEATURES
GENERAL DESCRIPTION
14-bit 15 MSPS ADC
No missing codes guaranteed
3-channel operation up to 15 MSPS
1-channel operation up to 12.5 MSPS
Correlated double sampling
1–6× programmable gain
±350 mV programmable offset
Input clamp circuitry
Internal voltage reference
Multiplexed byte-wide output (8 + 6 format)
3-wire serial digital interface
3 V/5 V digital I/O compatibility
28-Lead SOIC or SSOP
Low power CMOS: 385 mW (typ)
Power-down mode: <1 mW
The AD9822 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture designed
to sample and condition the outputs of trilinear color CCD
arrays. Each channel consists of an input clamp, correlated double
sampler (CDS), offset DAC, and programmable gain amplifier
(PGA) multiplexed to a high performance 14-bit ADC.
The CDS amplifiers may be disabled for use with sensors such
as contact image sensors (CIS) and CMOS active pixel sensors,
which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal
registers are programmed through a 3-wire serial interface and
provide adjustment of the gain, offset, and operating mode.
The AD9822 operates from a single 5 V power supply,
consumes 385 mW of power typically, and is packaged in a
28-lead SOIC or SSOP.
APPLICATIONS
Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals
FUNCTIONAL BLOCK DIAGRAM
VINR
AVSS
CML
CDS
CAPT
CAPB
AVDD
CDS
14:8
MUX
8
MUX
REGISTER
PGA
INPUT
CLAMP
BIAS
14
DOUT
CONFIGURATION
REGISTER
6
CDSCLK1
14-BIT
ADC
3:1
MUX
9-BIT
DAC
OFFSET
OEB
BAND GAP
REFERENCE
PGA
CDS
DRVSS
AD9822
9-BIT
DAC
VINB
DRVDD
PGA
9-BIT
DAC
VING
AVSS
9
RED
GREEN
BLUE
RED
GREEN
BLUE
CDSCLK2
SCLK
DIGITAL
CONTROL
INTERFACE
GAIN
REGISTERS
SLOAD
SDATA
OFFSET
REGISTERS
ADCCLK
00623-001
AVDD
Figure 1.
Rev. B
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