SHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
KEY FEATURES—PROCESSOR CORE
High performance signal processor for communications,
graphics and imaging applications
Super Harvard Architecture
4 independent buses for dual data fetch, instruction fetch,
and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball
plastic ball grid array (PBGA), 240-lead hermetic CQFP
package
RoHS compliant packages
40 MIPS, 25 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing)
Efficient program sequencing with zero-overhead looping:
Single-cycle loop setup
IEEE JTAG Standard 1149.1 Test Access Port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
CORE PROCESSOR
8
DAG1
4 32
8
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
ADDR
DATA
DATA
ADDR
ADDR
DATA
DAG2
4 24
JTAG
BLOCK 1
INSTRUCTION
CACHE
32 48-BIT
B LOCK 0
TIMER
DUAL-PORTED SRAM
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
IOD
48
24
IOA
17
EXTERNAL
PORT
ADDR BUS
MUX
32
7
TEST AND
EMULATION
32
MULTIPROCESSOR
INTERFACE
PM DATA BUS
BUS
CONNECT
(PX)
DM DATA BUS
48
DATA BUS
MUX
40/32
S
DATA
REGISTER
FILE
MULT
16
40-BIT
BARREL
SHIFTER
HOST PORT
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY
MAPPED)
ALU
48
4
6
CONTROL,
STATUS AND
DATA BUFFERS
SERIAL PORTS
(2)
LINK PORTS
(6)
6
36
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. H
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