FINAL
Am27C512
512 Kilobit (64 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
n Fast access time
n Latch-up protected to 100 mA from –1 V to
VCC + 1 V
— Speed options as fast as 55 ns
n High noise immunity
n Low power consumption
n Versatile features for simple interfacing
— 20 µA typical CMOS standby current
n JEDEC-approved pinout
— Both CMOS and TTL input/output compatibility
n Single +5 V power supply
— Two line control functions
n Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
n ±10% power supply tolerance standard
n 100% Flashrite™ programming
— Typical programming time of 8 seconds
GENERAL DESCRIPTION
The Am27C512 is a 512-Kbit, ultraviolet erasable programmable read-only memory. It is organized as 64K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, allowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), resulting in a typical programming time of 8 seconds.
BLOCK DIAGRAM
VCC
Data Outputs
DQ0–DQ7
VSS
CE#
A0–A15
Address
Inputs
Output Enable
Chip Enable
and
Prog Logic
Output
Buffers
Y
Decoder
OE#/VPP
Y
Gating
X
Decoder
524,288
Bit Cell
Matrix
08140J-1
Publication# 08140 Rev: J Amendment/+2
Issue Date: June 1, 1999
