PRELIMINARY
Am29040™
Advanced
Micro
Devices
High-Performance RISC Microprocessor
with Instruction and Data Caches
DISTINCTIVE CHARACTERISTICS
Full 32-bit architecture
3.3-V operation with 5-V-tolerant I/O
66.8 VAX MIPS sustained at 50 MHz
Low-power Snooze and Sleep modes
4-Kbyte, two-way set-associative data cache
Fully static
8-Kbyte, two-way set-associative instruction
cache
8-, 16-, or 32-bit ROM interface
Two cycle 32-bit multiplier for fast integer
math; three-cycle Multiply Accumulate (MAC)
function
Pin and bus compatibility with Am29030™ and
Am29035™ microprocessors
Burst-mode and page-mode access support
Binary compatibility with all 29K™ Family
microprocessors and microcontrollers
32-entry on-chip Memory Management Unit
with dual Translation Look-Aside Buffers
CMOS technology/TTL-compatible
Multiprocessor support
192 general-purpose registers
Instruction/data parity on external bus with
MMU control of parity checking on page basis
Fully pipelined
Data cache control on page basis
Three-address instruction architecture
MMU-programmable 16- or 32-bit data bus
width on page basis
4-Gbyte virtual address space with demand
paging
Streamlined system interface for simplified,
high-frequency operation
On-chip timer facility
33-, 40-, and 50-MHz CPU operating frequencies
Hardware instruction and data breakpoints for
advanced debugging support
Scalable Clocking™ feature with
optional clock doubling
Traceable Cache™ instruction and data cache
tracing feature
Digital delay-locked loop (DLL) feature for
accurate clocking control
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and Boundary Scan
Architecture implementation
Am29040 MICROPROCESSOR BLOCK DIAGRAM
Am29000R CPU
32 x 32 Multiplier
MMU
Addr
Inst
Data
8-Kbyte
Instruction Cache
(2x1Kx32) bits
Addr
4-Kbyte
Data Cache
(2x512x32) bits
Inst/Data
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you evaluate this product. AMD® reserves the right to change or discontinue work on this proposed product without notice.
Publication# 18459 Rev. B Amendment /0
Issue Date: June 1995 WWW: 6/7/95