PRELIMINARY
Am79C965
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for 486 and
Video Electronics Standards Association
(VESA) local buses
s Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
s Direct interface to the 486 local bus or VESA
VL-Bus
s Enhanced burst mode with support for Am486™
burst read/write operations
s Software-compatible with AMD’s Am7990
LANCE, Am79C90 C-LANCE, Am79C960
PCnet-ISA, Am79C961 PCnet-ISA+, Am79C961A
PCnet-ISA II, Am79C970A PCnet-PCI II, and
Am79C900 ILACC™ register and descriptor
architecture
s Compatible with Am2100/Am1500T and Novell®
NE2100/NE1500 driver software
s High-performance Bus Master architecture with
integrated DMA buffer management unit for low
CPU and bus utilization
s Built-in byte-swap logic supports both big and
little endian byte alignment
s Microwire™ EEPROM interface supports
jumperless design
s Single +5 V power supply operation
s Low-power, CMOS design with sleep modes
allows reduced power consumption for critical
battery-powered applications and Green PCs
s Look-Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of receive
frame
s Integrated Manchester encoder/decoder
s Individual 136-byte transmit and 128-byte
receive FIFOs provide frame buffering for
increased system latency tolerance and
support the following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision frames
s JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board-level production test
s Provides integrated attachment unit interface
(AUI) and 10BASE-T transceiver with automatic
port selection
s Automatic twisted-pair receive polarity
detection and automatic correction of the
receive polarity
s Optional byte padding to long-word boundary
on receive
s Dynamic transmit FCS generation
programmable on a frame-by-frame basis
s Internal/external loopback capabilities
s Supports the following types of network
interfaces:
— AUI to external 10BASE-2, 10BASE-5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to twisted-pair medium
s Supports LANCE/C-LANCE/PCnet-ISA general
purpose serial interface (GPSI)
s 160-pin PQFP package
GENERAL DESCRIPTION
The PCnet-32 single-chip 32-bit Ethernet controller is a
highly integrated Ethernet system solution designed to
address high-performance system application requirements. It is a flexible bus-mastering device that can be
used in any networking application, including networkready PCs, printers, fax modems, and bridge/router
Publication# 18219 Rev: C Amendment/0
Issue Date: January 1998
designs. The bus-master architecture provides high
data throughput in the system and low CPU and bus
utilization. The PCnet-32 controller is fabricated with
AMD’s advanced low-power CMOS process to provide
low operating and standby current for power-sensitive
applications.
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
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