PRELIMINARY
Am79C987
Hardware Implemented Management Information Base™
(HIMIB™) Device
DISTINCTIVE CHARACTERISTICS
s Provides repeater management functions,
complying with all options detailed in the layer
management for 10 Mbyte/s Baseband
Repeaters (IEEE 802.3k) standard
s Fully compatible with the Novell Hub
Management Interface (HMI) specification
s Provides additional IEEE MAU management
functions (802.3p draft)
s Interfaces directly with AMD’s Am79C981
Integrated Multiport Repeater Plus™ (IMR+™)
device to build a fully managed repeater
s Multiple HIMIB/IMR+ devices can be used in a
system
s 8-bit microprocessor interface allows attribute
access, interrupt control, and management
control
s Maskable interrupts for notification of status/
error reporting
s Internal “receive only” MAC tracks all address
information and monitors exception conditions
s Supports mapping of node source addresses to
port numbers, through implementing source
address match function
s Full 32-bit hardware-implemented counters
incur no additional software overhead to keep
network statistics
s Pinout allows simple board layout between
IMR+ and HIMIB devices
s 28-pin PLCC device in CMOS technology for low
power with a single +5 V supply
GENERAL DESCRIPTION
The Am79C987 Hardware Implemented Management
Information Base (HIMIB) device is a highly integrated
chip that simplifies building fully managed multiport repeaters. The device integrates all the necessary
counters, attributes, actions, and notifications specified
by the Layer Management for 10 Mbyte/s Baseband
Repeaters (IEEE 802.3k) standard, as well as additional features and enhancements, including functions
specific to 10BASE-T repeaters.
The HIMIB chip is designed to be used in conjunction
with AMD’s Integrated Multiport Repeater Plus (IMR+)
device. When connected to an IMR+ (Am79C981)
Publication# 17305 Rev: B Amendment/0
Issue Date: May 1994
device, the HIMIB chip provides complete repeater and
per-port statistics on demand from an 8-bit parallel interface. No external processor is required to keep track
of attributes locally, as full 32-bit counters are provided.
The HIMIB device implements a simple 8-bit microprocessor interface, allowing multiple HIMIB devices to be
used in a system. No additional logic is required for interfacing the HIMIB device to the IMR+ device.
The HIMIB chip is packaged in a 28-pin plastic leaded
chip carrier (PLCC). The device is fabricated in CMOS
technology and requires a single +5 V supply.
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
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