HD74HC564, HD74HC574
Octal D-type Flip-Flops (with 3-state outputs)
REJ03D0630-0200
(Previous ADE-205-510)
Rev.2.00
Mar 30, 2006
Description
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only
that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive
going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements.
Features
• High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC564P
HD74HC574P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
—
HD74HC564FPEL
HD74HC574FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
EL (2,000 pcs/reel)
PRSP0020DC-A
RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
HD74HC564RPEL
EL (1,000 pcs/reel)
SOP-20 pin (JEDEC)
Function Table
Output Control
Inputs
Clock
Q0 :
Q0 :
L
X
Data
HD74HC564
HD74HC574
H
L
L
L
L
H
Outputs
L
H
H
L
X
X
Q0
Z
Q0
Z
level of Q before the indicated Steady-sate input conditions were established.
complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 9
