HM628128B Series
1 M SRAM (128-kword × 8-bit)
ADE-203-243E (Z)
Rev. 5.0
Nov. 1997
Description
The Hitachi HM628128B is a CMOS static RAM organized 131,072-word × 8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS shrink process
technology. It offers low power standby power dissipation, therefore, it is suitable for battery backup
systems. The device, packaged in a 525 mil SOP or a 8 mm × 20 mm TSOP or a 600 mil plastic DIP is
available.
Features
• Single 5 V supply: 5.0 V ± 10%
• Access time: 70/75/85 ns (max)
• Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10 µW (typ) (L/L-SL version)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible all inputs and outputs
• Capability of battery backup operation (L/L-SL version)
2 chip selection for battery backup
