56V
PRELIMINARY
CY62256V
32K x 8 Static RAM
Features
ers. These devices have an automatic power-down feature,
reducing the power consumption by over 99% when deselected. The CY62256V family is available in the standard
450-mil-wide (300-mil body width) SOIC, TSOP, and reverse
TSOP packages.
• Low voltage range:
— 2.7V − 3.6V (62256V)
— 2.3V − 2.7V (62256V25)
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•
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An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
— 1.6V − 2.0V (62256V18)
Low active power and standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62256V family is composed of three high-performance
CMOS static RAM’s organized as 32,768 words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state driv-
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
Pin Configurations
SOIC
Top View
I/O0
INPUTBUFFER
I/O1
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
512x512
Y
ARRA
I/O3
I/O4
I/O5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
C62256V–2
CE
WE
I/O6
POWER
DOWN
COLUMN
DECODER
I/O7
A 12
A 11
A1
A0
A 14
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
A 13
OE
C62256V–1
7
6
8
9
5
4
3
2
10
11
12
13
14
15
16
17
18
1
28
27
26
25
24
23
22
TSOP I
Reverse Pinout
Top View
(not to scale)
19
20
21
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
•
3901 North First Street
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
C62256V–3
C62256V–4
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. **
20
19
18
17
16
15
14
13
12
11
10
9
8
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San Jose
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CA 95134 • 408-943-2600
Revised August 31, 2001
