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部品型式

CY7C1329-100AC

製品説明
仕様・特性

CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz device). • Supports 133-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined operation The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.2 ns (for 133-MHz device) — 5.5 ns (for 100-MHz device) • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes Byte Write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed Write circuitry. • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100-lead TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram MODE (A[1:0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[15:0] GW Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a Read cycle when emerging from a deselected state. 16 14 ADDRESS CE REGISTER D D BWE BW 3 Q 16 14 64K × 32 Memory Array DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS BW2 D Q DQ[15:8] BYTEWRITE REGISTERS D Q DQ[7:0] BYTEWRITE REGISTERS BW1 BW0 CE1 CE2 CE3 32 32 D ENABLE Q CE REGISTER CLK D Q ENABLE DELAY REGISTER CLK OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[31:0] Cypress Semiconductor Corporation Document #: 38-05279 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 31, 2004

ブランド

CYPRESS

会社名

Cypress Semiconductor

本社国名

U.S.A

事業概要

主力製品は、NOR型フラッシュ・メモリ、F-RAMおよびSRAM Traveoマイクロコントローラ、業界唯一のPSoCソリューション、アナログ回路、PMIC、CapSense capacitive touch-sensingコントローラ、Wireless BLE Bluetooth Low-Energy、そしてUSB connectivityソリューションである。 2015年にスパンション社と合併し、フラッシュメモリ、マイクロコントローラ、ミックスドシグナル製品およびアナログ製品も強化も行っています。

供給状況

 
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