MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC54/74HC574A
Octal 3-State
Noninverting D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC54/74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the Clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, all device outputs are forced to
the high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HC574A is identical in function to the HCT374A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC574A is the noninverting version of the HC564.
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
1
20
VCC
2
19
Q0
Q0
D1
3
18
Q1
Q1
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
CLOCK
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
Q2
Q3
Q4
NON–
INVERTING
OUTPUTS
Q5
Q6
Q7
GND
CLOCK
OUTPUT ENABLE
11
PIN 20 = VCC
PIN 10 = GND
1
FUNCTION TABLE
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
Inputs
Units
OE
L
L
L
H
Internal Gate Count*
66.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
0.0075
pJ
Speed Power Product
3/97
© Motorola, Inc. 1997
3–1
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
* Equivalent to a two–input NAND gate.
REV 7
Output
