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OP400GPZ

製品説明
仕様・特性

Quad Low Offset, Low Power Operational Amplifier OP400 Data Sheet FUNCTIONAL BLOCK DIAGRAMS OUTA 1 14 –IN A 2 + V+ 4 OP400 +IN B 5 –IN B 6 – + + – OUT B 7 13 –IN D V+ 4 11 V– +IN C –IN B 6 9 –IN C OUT B 7 OUT C 16 OUT D +IN A 3 +IN D 8 – + –IN A 2 10 – +IN A 3 OUT D 12 OUT A 1 – + + – NC 8 15 –IN D 14 +IN D 13 V– OP400 +IN B 5 00304-001 Low input offset voltage: 150 µV maximum Low offset voltage drift over –55°C to +125°C: 1.2 μV/°C maximum Low supply current (per amplifier): 725 µA maximum High open-loop gain: 5000 V/mV minimum Input bias current: 3 nA maximum Low noise voltage density: 11 nV/√Hz at 1 kHz Stable with large capacitive loads: 10 nF typical Available in die form 12 +IN C – + + – 11 –IN C 10 OUT C 9 NC NC = NO CONNECT Figure 1. 14-Pin Ceramic DIP (Y-Suffix) and 14-Pin Plastic DIP (P-Suffix) 00304-002 FEATURES Figure 2. 16-Pin SOIC (S-Suffix) GENERAL DESCRIPTION The OP400 is the first monolithic quad operational amplifier that features OP77-type performance. Precision performance is not sacrificed with the OP400 to obtain the space and cost savings offered by quad amplifiers. The OP400 features an extremely low input offset voltage of less than 150 µV with a drift of less than 1.2 µV/°C, guaranteed over the full military temperature range. Open-loop gain of the OP400 is more than 5 million into a 10 kΩ load, input bias current is less than 3 nA, CMR is more than 120 dB, and PSRR is less than 1.8 µV/V. On-chip Zener zap trimming is used to achieve the low input offset voltage of the OP400 and eliminates the need for offset nulling. The OP400 conforms to the industrystandard quad pinout, which does not have null terminals. The OP400 features low power consumption, drawing less than 725 µA per amplifier. The total current drawn by this quad amplifier is less than that of a single OP07, yet the OP400 offers significant improvements over this industry-standard op amp. Voltage noise density of the OP400 is a low 11 nV/√Hz at 10 Hz, half that of most competitive devices. The OP400 is an ideal choice for applications requiring multiple precision operational amplifiers and where low power consumption is critical. V+ BIAS VOLTAGE LIMITING NETWORK +IN OUT –IN 00304-003 V– Figure 3. Simplified Schematic (One of Four Amplifiers Is Shown) Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

ブランド

AD

会社名

Analog Devices

本社国名

U.S.A

事業概要

半導体デバイスを製造するアメリカの多国籍企業。特にADC、DAC、MEMS、DSPなどに強い。現在は 65nm から 3μm のプロセスルールの回路を設計している。

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