SN54ACT373, SN74ACT373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002
SN54ACT373 . . . J OR W PACKAGE
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 10 ns at 5 V
Inputs Are TTL-Voltage Compatible
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
1
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
20
2
11
1D
1Q
OE
VCC
SN54ACT373 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
2D
2Q
3Q
3D
4D
8Q
D
D
D
D
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
PDIP – N
TOP-SIDE
MARKING
Tube
SN74ACT373N
Tube
SN74ACT373DW
Tape and reel
SN74ACT373DWR
SOP – NS
Tape and reel
SN74ACT373NSR
ACT373
SSOP – DB
Tape and reel
SN74ACT373DBR
AD373
TSSOP – PW
Tape and reel
SN74ACT373PWR
AD373
CDIP – J
Tube
SNJ54ACT373J
SNJ54ACT373J
CFP – W
Tube
SNJ54ACT373W
SNJ54ACT373W
LCCC – FK
Tube
SNJ54ACT373FK
SOIC – DW
–40°C to 85°C
40°C
–55°C to 125°C
SN74ACT373N
ACT373
SNJ54ACT373FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
