128Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
NC
NC
DQ0
NC
NC
NC
DQ1
-
OPTIONS
MARKING
NC
-
• Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)
32M4
16 Meg x 8 (4 Meg x 8 x 4 banks)
16M8
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
t
• WRITE Recovery ( WR)
t
WR = “2 CLK”1
A2
• Package/Pinout
Plastic Package – OCPL2
54-pin TSOP II (400 mil)
TG
54-pin TSOP II (400 mil) Lead-free
P
60-ball FBGA (8mm x 16mm)
FB 3
60-ball FBGA (8mm x 16mm)Lead-free BB 3
60-ball FBGA (11mm x 13mm)
FC 3
60-ball FBGA (11mm x 13mm) Lead-free BC 3
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
-8E 3,4,5
7.5ns @ CL = 3 (PC133)
-75
7.5ns @ CL = 2 (PC133)
-7E
6.0ns @ CL=3 (x16 only)
-6A
• Self Refresh
Standard
None
Low power
L
• Operating Temperature Range
Commercial (0oC to +70oC)
None
Industrial (-40oC to +85oC)
IT 3
NOTE:
1.
2.
3.
4.
5.
NC
-
-
VDD
DQ0 DQ0
- VDDQ
NC DQ1
DQ1 DQ2
- VssQ
NC DQ3
DQ2 DQ4
- VDDQ
NC DQ5
DQ3 DQ6
- VssQ
NC DQ7
VDD
NC DQML
- WE#
- CAS#
- RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
-
x16 x8 x4
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4
Configuration
16 Meg x 8
8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
Bank Addressing
Column Addressing
4K
4K
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
1K (A0–A9)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
GRADE
-6A
-7E
-7E
-75
-8E 3,4,5
-75
-8E 3 ,4,5
Refer to Micron Technical Note: TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not recommended for new designs.
Shown for PC100 compatability.
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2* CL = 3* TIME
167 MHz
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
–
–
5.4ns
–
–
6ns
6ns
5.4ns
5.4ns
–
5.4ns
6ns
–
–
1.5ns
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_G.p65 – Rev. G; Pub. 10/03
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
