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SA35J
HIGH SPEED 2K X 16 DUAL-PORT SRAM IDT7133SA/LA IDT7143SA/LA Features ◆ ◆ ◆ High-speed access – Military: 35/55/70/90ns (max.) – Industrial: 25/55ns (max.) – Commercial: 20/25/35/45/55/70/90ns (max.) Low-power operation – IDT7133/43SA Active: 1150mW (typ.) Standby: 5mW (typ.) – IDT7133/43LA Active: 1050mW (typ.) Standby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only) BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation–2V data retention TTL-compatible; single 5V (±10%) power supply Available in 68-pin ceramic PGA, Flatpack, PLCC and 100pin TQFP Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram CE L R/W RUB CER R/W LLB R/WRLB R/WLUB OE R OE L I/O8L - I/O15L I/O CONTROL I/O0L - I/O7L I/O8R - I/O15R I/O CONTROL I/O0R - I/O 7R (1) BUSY R BUSYL(1) A10L A0L MEMORY ARRAY ADDRESS DECODER 11 CE L ADDRESS DECODER A10R A0R 11 ARBITRATION LOGIC CE R (IDT7133 ONLY) 2746 drw 01 NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. JANUARY 2012 1 ©2013 Integrated Device Technology, Inc. DSC 2746/14
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