SN74AVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES191C – MARCH 1999 – REVISED DECEMBER 1999
D
D
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Member of the Texas Instruments
Widebus ™ Family
EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC ™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
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D
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Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™)
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
0.8
OH
VCC = 1.8 V
0.4
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
V
V
OL
– Output Voltage – V
2.8
VCC = 3.3 V
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
VCC = 2.5 V
VCC = 1.8 V
–160 –144 –128 –112 –96
170
–80
–64 –48
–32
–16
0
IOH – Output Current – mA
Figure 1. Output Voltage vs Output Current
This 32-bit (dual-octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed
specifically for 1.65-V to 3.6-V VCC operation.
The SN74AVC32245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright © 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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PRODUCT PREVIEW
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