Freescale Semiconductor
Data Sheet: Technical Data
Document Number: P5020
Rev. 1, 03/2015
P5020/P5010
QorIQ P5020/P5010 Data
Sheet
The P5020 and P5010 QorIQ integrated communication
processor combines Power Architecture® processor cores
with high-performance data path acceleration logic and
network and peripheral bus interfaces required for
networking, telecom/datacom, wireless infrastructure, and
aerospace applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
NOTE
Unless otherwise stated, all parameters within this document
apply to both the P5020 and the P5010.
The chip includes the following function and features:
• Two e5500 Power Architecture cores (one on the P5010)
– Each core has a backside 512-Kbyte L2 Cache with ECC
– Three levels of instructions: User, Supervisor, and
Hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet endpoints
• 2-Mbyte CoreNet platform cache with ECC (one on the
P5010)
• One 10-Gigabit Ethernet (XAUI) controller
• Five 1-Gigabit Ethernet controllers
– 1 Gb/s SGMII, 2.5 Gb/s SGMII and RGMII interfaces
• Two 64-bit DDR3/3L SDRAM memory controllers with
ECC (one on the P5010)
• Multicore programmable interrupt controller (MPIC)
• Four I2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2013—2015 Freescale Semiconductor, Inc. All rights reserved.
FC-PBGA–1295
37.5 mm × 37.5 mm
•
•
•
•
•
•
•
•
•
Two 4-channel DMA engines
Enhanced local bus controller (eLBC)
Four PCI Express 2.0 controllers/ports
Two Serial RapidIO® controllers/ports (sRIO port)
v1.3-compliant with features of v2.1
Two serial ATA (SATA) 2.0 controllers
Enhanced secure digital host controller (SD/MMC)
Enhanced serial peripheral interfaces (eSPI)
2× full-speed USB 2.0 controllers with integrated PHYs
RAID 5 and 6 storage accelerator with support for
end-to-end data protection information
