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ISPLSI1016E-80LT44

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LeadFree Package Options Available! ispLSI 1016E ® In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay Logic A3 Array — Unused Product Term Shutdown Saves Power B1 A6 Global Routing Pool (GRP) B0 CLK 0139C1-isp N Description • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only R The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. FO — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality B4 B2 A5 EW — 100% Tested at Time of Manufacture D Q GLB D Q A7 — Non-Volatile B5 D Q B3 A4 — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable B6 ES IG N — Small Logic Block Size for Random Logic A2 D Output Routing Pool — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. D Q A1 Output Routing Pool B7 A0 — High-Speed Global Interconnect S — 96 Registers — Reprogram Soldered Device for Faster Prototyping I1 01 6E A • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. — Synchronous and Asynchronous Clocks LS — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement is p — Optimized Global Routing Pool Provides Global Interconnectivity U SE — Lead-Free Package Options Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016e_09 1 August 2006

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