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CY8C4247LQI-BL483

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PSoC® 4: PSoC 4XX7_BLE Family Datasheet ® Programmable System-on-Chip (PSoC ) General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4XX7_BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4XX7_BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Capacitive Sensing ■ 48-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 128 KB of flash with Read Accelerator ■ Up to 16 KB of SRAM 2.4-GHz RF transceiver with 50-Ω antenna drive ■ Digital PHY ■ Link Layer engine supporting master and slave modes ■ RF output power: –18 dBm to +3 dBm ■ RX sensitivity: –89 dBm ■ RX current: 16.4 mA ■ Received Signal Strength Indication (RSSI): 1-dB resolution Automatic hardware-tuning algorithm (SmartSense™) TX current: 15.6 mA at 0 dBm ■ Cypress-supplied software component makes capacitive-sensing design easy ■ ■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance ■ BLE Radio and Subsystem ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep-Sleep mode with four bits per pin memory ■ Two independent runtime reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Timing and Pulse-Width Modulation ■ Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode. ■ 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ ■ Serial Communication Programmable Analog ■ Segment LCD Drive Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIOs Programmable Digital 7 mm × 7 mm 56-pin QFN package ■ 3.51 mm × 3.91 mm 68-ball CSP package ■ Two low-power comparators that operate in Deep-Sleep mode ■ Any GPIO pin can be CapSense, LCD, analog, or digital Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable ■ Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapath ■ ■ Cypress-provided peripheral Component library, user-defined state machines, and Verilog input PSoC Creator™ Design Environment ■ Integrated design environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) ■ API components for all fixed-function and programmable peripherals Power Management ■ Active mode: 1.7 mA at 3-MHz flash program execution ■ Deep-Sleep mode: 1.3 µA with watch crystal oscillator (WCO) on ■ Hibernate mode: 150 nA with RAM retention ■ Stop mode: 60 nA Cypress Semiconductor Corporation Document Number: 001-90479 Rev. *L • Industry-Standard Tool Compatibility ■ 198 Champion Court After schematic entry, development can be done with ARM-based industry-standard development tools • San Jose, CA 95134-1709 • 408-943-2600 Revised April 12, 2016

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