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SI4734-D60-GU

製品説明
仕様・特性

Si4730/31/34/35-D60 B ROADCAST AM/FM/SW/LW R ADIO R ECEIVER Features                 Ordering Information: See page 31. Pin Assignments Si473x-D60 (QFN) DFS   Seven selectable AM channel filters AM/FM/SW/LW digital tuning EN55020 compliant No manual alignment necessary Programmable reference clock Adjustable soft mute control RDS/RBDS processor (Si4731/35) Digital audio out 2-wire and 3-wire control interface Integrated LDO regulator Wide range of ferrite loop sticks and air loop antennas supported QFN and SSOP packages RoHS compliant GPO3/[DCLK]   GPO2/[INT]   GPO1  Worldwide FM band support (64–108 MHz) Worldwide AM band support (520–1710 kHz) SW band support (Si4734/35) (2.3–26.1 MHz) LW band support (Si4734/35) (153–279 kHz) Excellent real-world performance Integrated VCO Advanced AM/FM seek tuning Automatic frequency control (AFC) Automatic gain control (AGC) Digital FM stereo decoder Programmable de-emphasis Advanced Audio Processing NC  20 19 18 17 16 Applications Table and portable radios Mini/micro systems  CD/DVD and Blu-ray players  Stereo boom boxes Modules for consumer electronics Clock radios  Mini HiFi and docking stations  Entertainment systems   NC   FMI 2 1 14 LOUT/[DFS] GND PAD AMI 4 13 ROUT/[DOUT] 8 9 10 SDIO RCLK 11 VA VD SEN Description 12 GND 7 SCLK RST 5 6 The Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete broadcast tuner and receiver function from antenna input to digital audio output. The device leverages the Silicon Labs broadcast proven digital low-IF architecture, enabling a cost-effective, digital audio platform for consumer electronic applications with high TDMA noise immunity, superior radio performance, and high fidelity audio power amplification. 15 DOUT RFGND 3 Si473x-D60(SSOP) LN A AMI AD C M ux LN A Rev. 1.2 8/13 VA 5 20 VD 6 19 RCLK 7 18 SDIO 17 SCLK 9 16 SEN DFS NC 10 15 RST G PO /D CLK NC 11 14 GND 12 13 GND RO UT DA C LO UT VD 1.62 - 3.6 V RST SEN AFC SDIO CO NTR O L INTER FAC E SCLK LD O DBYP 21 D SP VA GND 22 4 8 DA C AD C M ux RCLK + 3 GPO2/[INT] FMI DO UT DIG ITA L AU D IO LO W -IF AGC 2.7~5.5 V (Q FN ) 2.0~5.5 V (SSO P) GPO3/[DCLK] AMI RD S (S i4731/ 35) FM I AGC ROUT/[DOUT] RFGND Si473x-D60 R FG N D LOUT/[DFS] 23 NC A M / LW A NT 24 2 NC FM / SW AN T 1 DFS GPO1 Functional Block Diagram DOUT Copyright © 2013 by Silicon Laboratories This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. Si473x-D60

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SILICONLABS

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