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FM24C256-G
FM24C256 – 256K-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description Features FM24C256 is a 256Kbit CMOS non-volatile serial EEPROM organized as 32K x 8 bit memory. This device confirms to Extended IIC 2-wire protocol that allows accessing of memory in excess of 16Kbit on an IIC bus. This serial communication protocol uses a Clock signal (SCL) and a Data signal (SDA) to synchronously clock data between a master (e.g. a microcontroller) and a slave (EEPROM). FM24C256 is designed to minimize pin count and simplify PC board layout requirements. I Extended operating voltage: 2.7V to 5.5V FM24C256 offers hardware write protection where by the entire memory array can be write protected by connecting WP pin to V The entire memory then becomes unalterable until the WP pin is switched to V SS. I Up to 400 KHz clock frequency at 2.7V to 5.5V I Low power consumption — 0.5mA active current typical — 10µA standby current typical — 1µA standby current typical (L version) — 0.1µA standby current typical (LZ version) I Schmitt trigger inputs I 64 byte page write mode CC. I Self timed write cycle (6ms max) I Hardware Write Protection for the entire array “LZ” and “L” versions of FM24C256 offer very low standby current making them suitable for low power applications. This device is offered in SO and DIP packages. I Endurance: up to 100K data changes Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption. I Temperature range — Commercial: 0 °C to +70°C — Industrial (E): -40 °C to +85°C — Automotive (V): -40 °C to +125 °C I Data Retention: Greater than 40 years I Packages: 8-Pin DIP and 8-Pin SO Block Diagram VSS WRITE LOCKOUT VCC H.V. GENERATION TIMING &CONTROL WP START STOP LOGIC SDA CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR SCL XDEC A2 A1 A0 E2PROM ARRAY WORD ADDRESS COUNTER R/W YDEC CK DATA REGISTER DIN © 2001 Fairchild Semiconductor Corporation FM24C256 Rev. D.1 1 DOUT www.fairchildsemi.com FM24C256 – 256K-Bit Standard 2-Wire Bus Interface Serial EEPROM November 2001
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