HC55120, HC55121, HC55130, HC55140,
HC55142, HC55143, HC55150
ESIGNS
R N E W D NT
DED F O
N
ME
COMME
E PL ACE
at
N OT R E
NDED R
t Center
OMME
upporSheet
NO R EC
hnical S Data rsil.com/tsc
te
our Tec
contact ERSIL or www.in
NT
1-888-I
June 1, 2006
Low Power UniSLIC14 Family
Features
The UniSLIC14 is a family of Ultra Low Power SLICs. The
feature set and common pinouts of the UniSLIC14 family
positions it as a universal solution for: Plain Old Telephone
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in
the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local
Loop.
FN4659.13
• Ultra Low Active Power (OHT) < 60mW
The UniSLIC14 family achieves its ultra low power operation
through: Its automatic single and dual battery selection (based
on line length) and battery tracking anti clipping to ensure the
maximum loop coverage on the lowest battery voltage. This
architecture is ideal for power critical applications such as
ISDN NT1+, Pairgain and Wireless local loop products.
• Single/Dual Battery Operation
• Automatic Silent Battery Selection
• Power Management/Shutdown
• Battery Tracking Anti Clipping
• Single 5V Supply with 3V Compatible Logic
• Zero Crossing Ring Control
- Zero Voltage On/Zero Current Off
• Tip/Ring Disconnect
• Pulse Metering Capability
• 4 Wire Loopback
The UniSLIC14 family has many user programmable features.
This family of SLICs delivers a low noise, low component
count solution for Central Office and Loop Carrier universal
voice grade designs. The product family integrates advanced
pulse metering, test and signaling capabilities, and zero
crossing ring control.
• Programmable Current Feed
The UniSLIC14 family is designed in the Intersil “Latch” free
Bonded Wafer process. This process dielectrically isolates the
active circuitry to eliminate any leakage paths as found in our
competition’s JI process. This makes the UniSLIC14 family
compliant with “hot plug” requirements and operation in harsh
outdoor environments.
• Selectable Transmit Gain 0dB/-6dB
TRLY1
STATE
DECODER
AND
DETECTOR
LOGIC
RING AND TEST
RELAY DRIVERS
TRLY2
DT
DR
ZERO CURRENT
CROSSING
RING TRIP
DETECTOR
LOOP CURRENT
DETECTOR
GKD/LOOP LENGTH
DETECTOR
RING
BGND
AGND
LINE FEED
CONTROL
2-WIRE
INTERFACE
4-WIRE INTERFACE
VF SIGNAL PATH
VBH
VBL
VCC
C1
C2
C3
C4
C5
SHD
GKD_LVM
CRT_REV_LVM
POLARITY
REVERSAL
TIP
• Programmable Loop Detect Threshold
• Programmable On-Hook and Off-Hook Overheads
• Programmable Overhead for Pulse Metering
• Programmable Polarity Reversal Time
• 2 Wire Impedance Set by Single Network
• Loop and Ground Key Detectors
• On-Hook Transmission
• Common Pinout
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
RRLY
• Programmable Resistive Feed
BATTERY
SELECTION
AND
BIAS
NETWORK
PULSE METERING
SIGNAL PATH
SPM
1
ILIM
RSYNC_REV
ROH
CDC
RDC_RAC
RD
VTX
VRX
PTG
ZT
CH
• HC55121
- Polarity Reversal
• HC55130
- -63dB Longitudinal Balance
• HC55140
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2 Wire Loopback
- -63dB Longitudinal Balance
• HC55142
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2.2VRMS Pulse Metering
- 2 Wire Loopback
• HC55150
- Polarity Reversal
- Line Voltage Measurement
- 2.2VRMS Pulse Metering
- 2 Wire Loopback
Related Literature
• AN9871, User’s Guide for UniSLIC14 Eval Board
• AN9903, UniSLIC14 and TI TCM38C17
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2002, 2004-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.