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ispLSI 1048E
®
In-System Programmable High Density PLD
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
Output Routing Pool
— 96 I/O Pins, Twelve Dedicated Inputs
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D Q
A1
A2
A3
A4
Logic
Global Routing Pool (GRP)
D5
Array
D Q
D Q
GLB
D4
D3
D2
A5
D Q
A6
D1
D0
A7
— Functionally and Pin-out Compatible to ispLSI 1048C
D6
D
ES
IG
N
Output Routing Pool
— High-Speed Global Interconnects
S
A0
— 288 Registers
Output Routing Pool
Features
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Output Routing Pool
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
0139G1A-isp
EW
— tpd = 7.5 ns Propagation Delay
CLK
Description
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
N
— Non-Volatile
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
FO
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
R
— 100% Tested at Time of Manufacture
EA
— Reprogram Soldered Devices for Faster Prototyping
48
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
10
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
SI
— Synchronous and Asynchronous Clocks
is
pL
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
SE
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1048e_12
1
August 2006