CDC3S04
www.ti.com
SCAS883C – OCTOBER 2009 – REVISED AUGUST 2012
Quad Sine-Wave Clock Buffer With LDO
Check for Samples: CDC3S04
FEATURES
DESCRIPTION
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The CDC3S04 is a four-channel low-power low-jitter
sine-wave clock buffer. It can be used to buffer a
single master clock to multiple peripherals. The four
sine-wave outputs (CLK1–CLK4) are designed for
minimal channel-to-channel skew and ultralow
additive output jitter.
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1:4 Low-Jitter Clock Buffer
Single-Ended Sine-Wave Clock Input and
Outputs
Ultralow Phase Noise and Standby Current
Individual Clock Request Inputs for Each
Output
On-Chip Low-Dropout Output (LDO) for LowNoise TCXO Supply
Serial I2C Interface (Compatible With HighSpeed Mode, 3.4 Mbit/s)
1.8-V Device Power Supply
Wide Temperature Range, –40°C to 85°C
ESD Protection: 2 KV HBM, 750 V CDM, and
100 V MM
Small 20-Pin Chip-Scale Package: 0.4-mm
Pitch WCSP (1.6 mm × 2 mm)
Each output has its own clock request inputs which
enables the dedicated clock output. These clock
requests are active-high (can also be changed to be
active-low via I2C), and an output signal is generated
that can be sent back to the master clock to request
the clock (MCLK_REQ). MCKL_REQ is an opensource output and supports the wired-OR function
(default mode). It needs an external pulldown resistor.
MCKL_REQ can be changed to wired-AND or pushpull functionality via I2C.
The CDC3S04 also provides an I2C interface (Hsmode) that can be used to enable or disable the
outputs, select the polarity of the REQ inputs, and
allow control of internal decoding.
APPLICATIONS
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The CDC3S04 features an on-chip high-performance
LDO that accepts voltages from 2.3 V to 5.5 V and
outputs a 1.8-V supply. This 1.8-V supply can be
used to power an external 1.8-V TCXO. It can be
enabled or disabled for power saving at the TCXO.
Cellular Phones
Smart Phones
Mobile Handsets
Portable Systems
Wireless Modems Including GPS, WLAN, WBT, D-TV, DVB-H, FM Radio, WiMAX, and
System Clock
VDD_DIG
VDD_ANA
WCSP
LDO
VBAT
VLDO
REQ1
RESET
Reset
A
CLK1
B
REQ2
MCLK_IN
CLK2
CLK3
REQ4
ADR_A0
MCLK_
RESET
IN
REQ1
CLK1
VDD_
ANA
GND_
ANA
REQ4
CLK4
REQ3
CLK3
D
VDD_
DIG
GND_ MCLK_
REQ
DIG
ADR_
A0
E
VLDO
VBAT
SDAH
SCLH
1
MCLK_REQ
SDAH
CLK2
C
2
3
4
REQ3
SCLH
REQ2
2
CLK4
I C
Control
Register
Top View
(Solder Ball Underneath)
Decoder
GND_DIG
GND_ANA
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
