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4043B

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MC14043B, MC14044B CMOS MSI Quad R−S Latches The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. http://onsemi.com MARKING DIAGRAMS PDIP−16 P SUFFIX CASE 648 Features • Double Diode Input Protection • Three−State Outputs with Common Enable • Outputs Capable of Driving Two Low−power TTL Loads or One • • 16 MC140xxBCP AWLYYWWG 1 16 Low−Power Schottky TTL Load Over the Rated Temperature Range Supply Voltage Range = 3.0 Vdc to 18 Vdc Pb−Free Packages are Available* SOIC−16 D SUFFIX CASE 751B 140xxBG AWLYWW 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 16 SOEIAJ−16 F SUFFIX CASE 966 MC140xxB ALYWG 1 xx A WL, L YY, Y WW, W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 6 1 Publication Order Number: MC14043B/D

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