Very Low Power/Voltage CMOS SRAM
2M X 8 bit
BSI
FEATURES
BS62LV1603
GENERAL DESCRIPTION
• Vcc operation voltage : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
The BS62LV1603 is a high performance , very low power CMOS Static
Random Access Memory organized as 2048K words by 8 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
3.0uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
The BS62LV1603 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1603 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
BS62LV1603EC
BS62LV1603FC
BS62LV1603EI
BS62LV1603FI
O
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
55ns : 3.0~3.6V
70ns : 2.7~3.6V
POWER DISSIPATION
STANDBY
Operating
( I CCSB1, Max )
PKG TYPE
( ICC , Max )
Vcc=3V
55ns
Vcc=3V
Vcc=3V
70ns
2.7V ~ 3.6V
55 / 70
10uA
-40 O C to +85O C
2.7V ~ 3.6V
55 / 70
20uA
TSOP2-44
BGA-48-0912
TSOP2-44
37mA
BGA-48-0912
45mA
46mA
36mA
FUNCTIONAL BLOCK DIAGRAM
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BS62LV1603EC
BS62LV1603EI
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
1
A
SPEED
( ns )
+0 C to +70 C
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
A20
WE
A19
A18
A17
A16
A15
Vcc
RANGE
2
3
4
5
OE
A0
A1
A2
CE2
B
NC
NC
A3
A4
CE1
NC
C
D0
NC
A5
A6
NC
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D2
VCC
A16
D6
VSS
F
D3
NC
A14
A15
NC
D7
G
NC
A20
A12
A13
WE
A18
A8
A9
A10
A11
Input
Buffer
24
4096
Row
Memory Array
4096 X 4096
Decoder
8
8
Data
Input
Buffer
Data
Output
Buffer
Column I/O
8
8
Write Driver
Sense Amp
NC
H
Address
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
6
NC
A20
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
A19
CE1
CE2
WE
OE
Vdd
Gnd
512
Column Decoder
18
Control
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1603
1
Revision 1.1
Jan.
2004
